Application of Butterfly Clos-Network in Network-on-Chip

نویسندگان

  • Hui Liu
  • Linquan Xie
  • Jiansheng Liu
  • Lei Ding
چکیده

This paper studied the topology of NoC (Network-on-Chip). By combining the characteristics of the Clos network and butterfly network, a new topology named BFC (Butterfly Clos-network) network was proposed. This topology integrates several modules, which belongs to the same layer but different dimensions, into a new module. In the BFC network, a bidirectional link is used to complete information exchange, instead of information exchange between different layers in the original network. During the routing period, other nondestination nodes can be used as middle stages to transfer data packets to complete the routing mission. Therefore, this topology has the characteristic of multistage. Simulation analyses show that BFC inherits the rich path diversity of Clos network, and it has a better performance than butterfly network in throughput and delay in a quite congested traffic pattern.

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

Application Mapping onto Network-on-Chip using Bypass Channel

Increasing the number of cores integrated on a chip and the problems of system on chips caused to emerge networks on chips. NoCs have features such as scalability and high performance. NoCs architecture provides communication infrastructure and in this way, the blocks were produced that their communication with each other made NoC. Due to increasing number of cores, the placement of the cores i...

متن کامل

Adaptive Load Balanced Routing for 2-Dilated Flattened Butterfly Switching Network

High-radix networks such as folded-Clos outperform other low radix networks in terms of cost and latency. The 2-dilated flattened butterfly (2DFB) network is a nonblocking high-radix network with better path diversity and reduced diameter compared to the folded-Clos network. In this paper, we introduce an adaptive load balanced routing algorithm that is designed to exploit all the positive topo...

متن کامل

Design and Implementation of Multistage Interconnection Networks for SoC Networks

In this paper the focus is on a family of Interconnection Networks (INs) known as Multistage Interconnection Networks (MINs). When it is exploited in Network-on-Chip (NoC) architecture designs, smaller circuit area, lower power consumption, less junctions and broader bandwidth can be achieved. Each MIN can be considered as an alternative for an NoC architecture design for its simple topology an...

متن کامل

Butterfly vs. Unidirectional Fat-Trees for Networks-on-Chip: not a Mere Permutation of Outputs∗

Bidirectional topologies are usually preferred over unidirectional ones. However, recent works have demonstrated that RUFT, a traffic-balancing routing algorithm on a Unidirectional Multistage Network (UMIN), can perform as well as a Bidirectional Multistage Network, but significantly reducing both implementation and operating costs. RUFT is a simplification of the k-ary n-tree topology, the mo...

متن کامل

Reliability and Performance Evaluation of Fault-aware Routing Methods for Network-on-Chip Architectures (RESEARCH NOTE)

Nowadays, faults and failures are increasing especially in complex systems such as Network-on-Chip (NoC) based Systems-on-a-Chip due to the increasing susceptibility and decreasing feature sizes. On the other hand, fault-tolerant routing algorithms have an evident effect on tolerating permanent faults and improving the reliability of a Network-on-Chip based system. This paper presents reliabili...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

عنوان ژورنال:

دوره 2014  شماره 

صفحات  -

تاریخ انتشار 2014